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RT8004A 1 ds8004a-03 march 2011 www.richtek.com features z z z z z high efficiency : up to 95% z z z z z low quiescent current : 100 a z z z z z low r ds(on) internal switches : 75m z z z z z programmable frequency : 300khz to 4mhz z z z z z no schottky diode required z z z z z 0.8v reference allows low output voltage z z z z z low dropout operation : 100% duty cycle z z z z z synchronizable switching frequency z z z z z power good output voltage monitor z z z z z over temperature protection z z z z z rohs compliant and 100% lead (pb)-free applications z portable instruments z battery-powered equipment z notebook computers z distributed power systems z ip phones z digital cameras 4.5a, 4mhz, synchronous step-down regulator ordering information general description the RT8004A is a high efficiency synchronous, step-down dc/dc converter. with an input voltage range is from 2.7v to 5.5v, it can provide adjustable regulated output voltage from 0.8v to 5v while delivering up to 4.5a of output current. the internal power switch with 75m on-resistance increases efficiency and eliminates the need for an external schottky diode. switching frequency is either set by an external resistor or synchronized to an external clock. 100% duty cycle provides low dropout operation, hence extending battery life in portable systems. external compensation allows the transient response to be optimized over a wide range of loads and output capacitors. the RT8004A operates in forced continuous mode which reduces noise and rf interference. 100% duty cycle in low dropout operation further maximizes battery life. note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. marking information RT8004A gcpymdnn 01=ym dnn RT8004Agcp : product number ymdnn : date code tssop-16 (exposed pad) 01= : product code ymdnn : date code vqfn-16l 4x4 RT8004A package type cp : tssop-16 (exposed pad) qv : vqfn-16l 4x4 (v-type) lead plating system p : pb free g : green (halogen free and pb free)
RT8004A 2 ds8004a-03 march 2011 www.richtek.com typical application circuit pin configurations (top view) vdd pgood comp fb rt sync en/ss gnd pvdd lx lx pgnd pgnd lx lx pvdd 4 2 3 5 7 6 8 13 15 14 12 10 11 9 16 gnd 17 tssop-16 (exposed pad) 17 comp lx sync rt fb lx pgnd pgnd lx en/ss gnd pvdd lx pgood vdd pvdd 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 gnd vqfn-16l 4x4 vdd lx gnd RT8004A pgood comp r pg 100k r th 10k c th 1000pf r2 240k r ocs 309k r ss 4.7m c ss 470pf pgnd c out 47f v out 2.5v/4.5a fb rt sync en/ss pvdd pgood c1 22pf r1 510k l1 1h external clock 47f v in 2.7v to 5.5v c in1 10f x 2
RT8004A 3 ds8004a-03 march 2011 www.richtek.com functional pin description pin no. tssop-16 (exposed pad) vqfn-16l 4x4 pin name pin function 1 15 vdd signal input supply. decouple this pin to gnd with a capacitor. normally vdd is equal to pvdd. 2 16 pgood power good indicator. this pin is an open-drain logic output that is pulled to ground when the output voltage is not within 12.5% of regulation point. 3 1 comp error amplifier compensation pin. the current comparator threshold increases with this control voltage. connect external compensation elements to this pin to stabilize the control loop. 4 2 fb feedback pin. receives the feedback voltage from a resistive voltage-divider connected across the output. 5 3 rt oscillator resistor input. connecting a resistor to ground from this pin sets the switching frequency. 6 4 sync external clock synchronization input. the internal oscillator can be synchronized to an external clock applied to this pin. if not in use, please connect this pin to vdd or gnd. 7 5 en/ss enable control and soft-start input. forcing this pin below 0.5v shuts down the RT8004A. in shutdown, all functions are disabled, drawing < 1 a of supply current. a capacitor to ground from this pin sets the ramp time to full output current. 8, 17 (exposed pad) 6, 17 (exposed pad) gnd signal ground. all small-signal components, compensation components and the exposed pad on the bottom side of the ic should connect to this ground, which in turn connects to pgnd at one point. 9, 16 7, 14 pvdd power input supply. decouple this pin to pgnd with a capacitor. 10,11, 14, 15 8, 9, 12, 13 lx internal power mosfet switch output. connect this pin to the inductor. 12, 13 10, 11 pgnd power ground. connect this pin close to the terminal of c in and c out .
RT8004A 4 ds8004a-03 march 2011 www.richtek.com operation main control loop the RT8004A is a monolithic, constant-frequency, current mode step-down dc/dc converter. during normal operation, the internal top power switch (p-mosfet) is turned on at the beginning of each clock cycle. current in the inductor increases until the peak inductor current reaches the value defined by the voltage on the comp pin. the error amplifier adjusts the voltage on the comp pin by comparing the feedback signal from a resistive voltage divider on the fb pin with an internal 0.8v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error amplifier raises the comp voltage until the average inductor current matches the new load current. when the top power mosfet shuts off, the synchronous power switch (n-mosfet) turns on until either the bottom current limit is reached or the next clock cycle begins. the bottom current limit is set at ? 2a. the operating frequency is set by an external resistor connected between the rt pin and ground. the practical switching frequency can range from 300khz to 4mhz. power good comparators will pull the pgood output low if the output voltage comes out of regulation by 12.5%. in an overvoltage condition, the top power mosfet is turned off and the bottom power mosfet is switched on until either the overvoltage condition clears or the bottom mosfet ? s current limit is reached. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on- time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-mosfet and the inductor. function block diagram oscillator v ref control logic output clamp ext_ss driver nisen bg slope com isen int_ss otp por n-mosfet i limit 0.9v 0.7v 0.4v sd oc limit extsyn ea por 0.8v pvdd lx pgnd pgood 0.8v vdd en/ss fb comp sync rt gnd
RT8004A 5 ds8004a-03 march 2011 www.richtek.com absolute maximum ratings (note 1) z supply input voltage --------------------------------------------------------------------------------------------- ? 0.3v to 6v z lx pin switch voltage ------------------------------------------------------------------------------------------- ? 0.3v to (pvdd + 0.3v) z other i/o pin v oltages ------------------------------------------------------------------------------------------ ? 0.3v to (v dd + 0.3v) z power dissipation, p d @ t a = 25 c tssop-16 (exposed pad) ------------------------------------------------------------------------------------- 2.128w vqfn-16l 4x4 ---------------------------------------------------------------------------------------------------- 1.852w z package thermal resistance (note 2) tssop-16 (exposed pad), ja ------------------------------------------------------------------------------- 45 c/w tssop-16 (exposed pad), jc ------------------------------------------------------------------------------- 30 c/w vqfn-16l 4x4, ja ----------------------------------------------------------------------------------------------- 54 c/w vqfn-16l 4x4, jc ---------------------------------------------------------------------------------------------- 7 c/w z lead temperature (soldering, 10 sec.) -- -------------------------------------------------------------------- 260 c z junction temperature -------------------------------------------------------------------------------------------- 150 c z storage temperature range ----------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------------------- 2kv mm (ma chine mode) --------------------------------------------------------------------------------------------- 200v recommended operating conditions (note 4) z supply input voltage --------------------------------------------------------------------------------------------- 2.7v to 5.5v z ambient temperature range ----------------------------------------------------------------------------------- ? 40 c to 85 c z junction temperature range ----------------------------------------------------------------------------------- ? 40 c to 125 c low supply operation the RT8004A is designed to operate down to an input supply voltage of 2.7v. one important consideration at low input supply voltages is that the r ds(on) of the p-mosfet and n-mosfet power switches increases. the user should calculate the power dissipation when the RT8004A is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. slope compensation and inductor peak current slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal. normally, the maximum inductor peak current is reduced when slope compensation is added. in the RT8004A, however, separated inductor current signals are used to monitor over current condition and minimum peak current. this keeps the maximum output current and minimum peak current relatively constant regardless of duty cycle. short circuit protection when the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. a current runaway detector is used to monitor inductor current. as current increases beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring.
RT8004A 6 ds8004a-03 march 2011 www.richtek.com electrical characteristics (v dd = 3.3v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit feedback reference voltage v ref (note 5) 0.784 0.8 0.816 v feedback leakage current i fb -- -- 0.4 a active, v fb = 0.78v, not switching 180 400 520 a input dc bias current shutdown, v en < 0.1v (note 5) -- -- 1 a reference voltage line regulation v in = 2.7v to 5.5v (note 5) -- 0.04 0.5 %/v output voltage load regulation measured in servo loop, v comp = 1.2v to 1.6v (note 5) -- 0.05 0.2 % power good power good range -- 12.5 15 % power good pull-down resistance -- -- 120 r osc = 309k 0.8 1 1.2 mhz switching frequency range f osc switching frequency range 0.3 -- 4 mhz sync frequency range (note 6) 0.3 -- 4 mhz switch on-resistance, high r pfet i lx = 1a 45 75 110 m switch on-resistance, low r nfet i lx = 1a 45 69 100 m peak current limit i lim 5 5.5 -- a vdd rising 2.25 2.52 2.7 v under voltage lockout threshold hysteresis -- 0.15 -- v sw leakage current v en = 0v, v in = 5.5v -- -- 1 a en/ss leakage current -- -- 1 a enable threshold v en 0.65 -- 0.95 v note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the packages. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. specifications over the ? 40 c to 85 c operation ambient temperature range are assured by design, characterization and correlation with statistical process controls. note 6. the external synchronous frequency must be equal to 1 to 1.3 times of the internal setting frequency. the switching frequency range is guaranteed by design but not production tested.
RT8004A 7 ds8004a-03 march 2011 www.richtek.com to be continued typical operating characteristics output voltage vs. input voltage 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.5 3.8 4.0 4.3 4.5 4.8 5.0 5.3 5.5 input voltage (v) output voltage (v) i out = 0a, v out = 3.3v output voltage vs. output current 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 output current (a) output voltage (v) v in = 5v, v out = 3.3v input voltage vs. temperature 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 -50 -25 0 25 50 75 100 125 temperature (c) input voltage (v) rising v in = 3.3v, v out = 1.2v falling frequency vs. temperature 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 -50 -25 0 25 50 75 100 125 temperature (c) frequency (mhz) 1 v in = 5v v in = 3.3v v out = 1.2v, i out = 0.3a output current limit vs. temperature 4.0 4.3 4.5 4.8 5.0 5.3 5.5 5.8 6.0 6.3 6.5 6.8 7.0 -50 -25 0 25 50 75 100 125 temperature (c) output current limit (a ) v in = 5v v in = 3.3v v out = 1.2v efficiency vs. output current 50 55 60 65 70 75 80 85 90 95 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 output current (a) efficiency (%) v in = 5v, v out = 3.3v
RT8004A 8 ds8004a-03 march 2011 www.richtek.com power on from v in time (2.5ms/div) i in (5a/div) v lx (2v/div) v in (5v/div) v in = 5v, v out = 3.3v, i out = 4.5a output ripple time (500ns/div) v out (10mv/div) v lx (2v/div) v in = 5v, v out = 3.3v, i out = 3a output ripple time (500ns/div) v out (10mv/div) v in = 5v, v out = 3.3v, i out = 0a v lx (2v/div) load transient response time (100 s/div) v out (100mv/div) v in = 5v, v out = 3.3v, i out = 0.1a to 3a i out (5a/div) load transient response time (100 s/div) v out (100mv/div) v in = 5v, v out = 1.2v, i out = 0.1a to 3a i out (5a/div) reference voltage vs. temperature 0.780 0.785 0.790 0.795 0.800 0.805 0.810 0.815 0.820 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) v in = 5v v in = 3.3v v out = 1.2v, i out = 0.3a
RT8004A 9 ds8004a-03 march 2011 www.richtek.com 1 v v v v i i out in in out out(max) rms ? = application information the basic RT8004A application circuit is shown in typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . operating frequency selection of the operating frequency is a tradeoff between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves efficiency by reducing internal gate charge and switching losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency of the RT8004A is determined by an external resistor that is connected between the rt pin and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. although frequencies as high as 4mhz are possible, the minimum on-time of the RT8004A imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 110ns. therefore, the minimum duty cycle is equal to 100 x 110ns x f(hz). inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increa ses with higher v in and decreases with higher inductance. having a lower ripple current reduces the esr losses in the output capacitors and output voltage ripple. highest efficiency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire and, therefore higher copper loss. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and saturation prevention. ferrite core material saturates ? hard ? , which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and don ? t radiate energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/emi requirements. c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by : ? ? ? ? ? ? ? ? ? ? ? ? ? = in out out l v v 1 l f v i ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = in(max) out l(max) out v v 1 i f v l
RT8004A 10 ds8004a-03 march 2011 www.richtek.com output voltage programming the output voltage is set by an external resistive voltage- divider according to the following equation : the resistive voltage-divider allows the fb pin to sense a fraction of the output voltage as shown in figure 1. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not result in much difference. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : the output ripple is highest at maximum input voltage since i l inc reases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. frequency synchronization the RT8004A ? s internal oscillator can be synchronized to an external clock signal. during synchronization, the high side mosfet turn-on is locked to the falling edge of the external frequency source. the synchronization frequency range is from 300khz to 4mhz. synchronization only occurs if the external frequency is greater than the frequency set by the external resistor. because slope compensation is generated by the oscillator ? s rc circuit, the external frequency should be set 25% higher than the frequency set by the external resistor to ensure that adequate slope compensation is present. soft-start the en/ss pin provides a means to shut down the RT8004A as well as a timer for soft-start. pulling the en/ ss pin below 0.5v places the RT8004A in a low quiescent current shutdown state (iq < 1 a). the RT8004A contains an internal soft-start clamp that ? ? ? ? ? ? + out l out 8fc 1 esr i v out r1 v0.8v (1) r2 =+ figure 1. setting the output voltage RT8004A gnd fb r2 r1 v out
RT8004A 11 ds8004a-03 march 2011 www.richtek.com gradually raises the clamp on comp after the en/ss pin is pulled above 0.8v. the full current range becomes available on comp after 1024 switching cycles. if a longer soft-start period is desired, the clamp on comp can be set externally with a resistor and capacitor on the en/ss pin as shown in typical application circuit. the soft-start duration can be calculated by using the following formula: thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT8004A, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for tssop-16 (exposed pad) packages, the thermal resistance, ja , is 47 c/w on a standard jedec 51-7 four-layer thermal test board. for vqfn-16l 4x4 packages, the thermal resistance, ja , is 54 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (47 c/w) = 2.128w for tssop-16 (exposed pad) package p d(max) = (125 c ? 25 c) / (54 c/w) = 1.852w for vqfn-16l 4x4 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the RT8004A packages, the derating curves in figure 2 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. (s) ) 1.8v v v ln( x c x r t in in ss ss ss ? = layout considerations follow the pcb layout guidelines for optimal performance of RT8004A. ` a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the gnd pin at one point that is then connected to the pgnd pin close to the ic. the exposed pad should be connected to gnd. ` connect the terminal of the input capacitor(s), c in , as close as possible to the pvdd pin. this capacitor provides the ac current into the internal power mosfets. ` lx node is with high frequency voltage swing and should be kept small area. keep all sensitive small-signal nodes away from lx node to prevent stray capacitive noise pick-up. ` flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. you can connect the copper areas to any dc net (pvin, svin, v out , pgnd, sgnd, or any other dc rail in your system). ` connect the fb pin directly to the feedback resistors. the resistor divider must be connected between v out and gnd. figure 2. derating curves for RT8004A package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 vqfn-16l 4x4 tssop-16 (exposed pad) four-layer pcb
RT8004A 12 ds8004a-03 march 2011 www.richtek.com outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 1.000 1.200 0.039 0.047 a1 0.000 0.150 0.000 0.006 a2 0.800 1.050 0.031 0.041 b 0.190 0.300 0.007 0.012 d 4.900 5.100 0.193 0.201 e 0.65 0.026 e 6.300 6.500 0.248 0.256 e1 4.300 4.500 0.169 0.177 l 0.450 0.750 0.018 0.030 u 2.000 3.000 0.079 0.118 v 2.000 3.000 0.079 0.118 16-lead tssop (exposed pad) plastic package l e1 e e a a2 a1 b d (bottom of package) exposed thermal pad u v
RT8004A 13 ds8004a-03 march 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com a a1 a3 d e 1 d2 e2 l b e see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.800 1.000 0.031 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.250 0.380 0.010 0.015 d 3.950 4.050 0.156 0.159 d2 2.000 2.450 0.079 0.096 e 3.950 4.050 0.156 0.159 e2 2.000 2.450 0.079 0.096 e 0.650 0.026 l 0.500 0.600 0.020 0.024 v-type 16l vqfn 4x4 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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